DISPS-P1: DSP Implementation I |
| Session Type: Poster
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| Time: Monday, March 21, 13:00 - 15:00
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| Location: CC: Poster 7
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| Chair: Andy Wu, National Taiwan University
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DISPS-P1.1: SIMULATION OF DSP ALGORITHMS ON FIXED POINT ARCHITECTURES |
| Keith Cullen; University College Dublin |
| Guenole Silvestre; University College Dublin |
| Neil Hurley; University College Dublin |
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DISPS-P1.2: DESIGN OF SIGMA-DELTA MODULATORS WITH ARBITRARY TRANSFER FUNCTIONS |
| Yongtao Wang; Purdue University |
| Khurram Muhammad; Texas Instruments |
| Kaushik Roy; Purdue University |
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DISPS-P1.3: ACCURACY EVALUATION OF FIXED-POINT APA ALGORITHM |
| Romuald Rocher; ENSSAT / IRISA |
| Daniel Menard; ENSSAT / IRISA |
| Olivier Sentieys; ENSSAT / IRISA |
| Pascal Scalart; ENSSAT / IRISA |
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DISPS-P1.4: A MORE EFFICIENT AND FLEXIBLE DSP DESIGN FLOW FROM MATLAB-SIMULINK |
| Philippe Coussy; LESTER Lab. / UBS University |
| Gwenole Corre; LESTER Lab. / UBS University |
| Pierre Bomel; LESTER Lab. / UBS University |
| Eric Senn; LESTER Lab. / UBS University |
| Eric Martin; LESTER Lab. / UBS University |
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DISPS-P1.5: RAPID GENERATION OF HARDWARE FUNCTIONALITY IN HETEROGENEOUS PLATFORMS |
| Darren Reilly; Queen's University Belfast |
| Roger Woods; Queen's University Belfast |
| John McAllister; Queen's University Belfast |
| Richard Walke; QinetiQ Ltd. |
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DISPS-P1.6: DYNAMIC CONFIGURATION OF DATAFLOW GRAPH TOPOLOGY FOR DSP SYSTEM DESIGN |
| Dong-Ik Ko; University of Maryland, College Park |
| Shuvra S. Bhattacharyya; University of Maryland, College Park |
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DISPS-P1.7: DEADLOCK DETECTION FOR DISTRIBUTED PROCESS NETWORKS |
| Alex Olson; University of Texas, Austin |
| Brian Evans; University of Texas, Austin |
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DISPS-P1.8: A PARALLEL ARCHITECTURE FOR THE ICA ALGORITHM: DSP PLANE OF A 3-D HETEROGENEOUS SENSOR |
| Vijay Jain; University of South Florida |
| Sanjukta Bhanja; University of South Florida |
| Glenn Chapman; Simon Fraser University |
| Lavanya Doddannagari; University of South Florida |
| Nguyen Nguyen; University of South Florida |
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DISPS-P1.9: DESIGN AND AUTOMATIC CODE GENERATION OF THE LMS ALGORITHM FOR SIMD SIGNAL PROCESSORS |
| Juan Pablo Robelly; Technische Universität Dresden |
| Gordon Cichon; Technische Universität Dresden |
| Hendrik Seidel; Technische Universität Dresden |
| Gerhard Fettweis; Technische Universität Dresden |
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DISPS-P1.10: OPTIMIZING DSP SCHEDULING VIA ADDRESS ASSIGNMENT WITH ARRAY AND LOOP TRANSFORMATION |
| Chun Xue; University of Texas, Dallas |
| Zili Shao; University of Texas, Dallas |
| Ying Chen; University of Texas, Dallas |
| Edwin Sha; University of Texas, Dallas |
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DISPS-P1.11: A GENERALIZED CACHED-FFT ALGORITHM |
| Bevan Baas; University of California, Davis |
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DISPS-P1.12: MEMORY ANALYSIS OF VLSI ARCHITECTURE FOR 5/3 AND 1/3 MOTION-COMPENSATED TEMPORAL FILTERING |
| Chao-Tsung Huang; National Taiwan University |
| Ching-Yeh Chen; National Taiwan University |
| Yi-Hau Chen; National Taiwan University |
| Liang-Gee Chen; National Taiwan University |
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DISPS-P1.13: MOTION COMPENSATION MEMORY ACCESS OPTIMIZATION STRATEGIES FOR H.264/AVC DECODER |
| RongGang Wang; Chinese Academy of Sciences |
| JinTao Li; Chinese Academy of Sciences |
| Chao Huang; Chinese Academy of Sciences |
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DISPS-P1.14: IMAGE PROCESSING SYSTEM USING A PROGRAMMABLE TRANSFORM IMAGER |
| Jungwon Lee; Georgia Institute of Technology |
| Abhishek Bandyopadhyay; Georgia Institute of Technology |
| Ismail Baskaya; Georgia Institute of Technology |
| Ryan Robucci; Georgia Institute of Technology |
| Paul Hasler; Georgia Institute of Technology |
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